1. Field of the Invention
The present invention relates to a semiconductor storage device and a semiconductor integrated circuit and, more particularly, to an FBC (Floating Body Cell) memory for storing information by accumulating majority carriers in a floating body of a field effect transistor (FET).
2. Related Art
It is concerned that as a DRAM cell constructed by a conventional one transistor and one capacitor having a trench capacitor and a stacked capacitor is becoming smaller, it is becoming difficult to fabricate the DRAM cell. As a memory cell which can replace such a DRAM cell, a new memory cell, an FBC, for storing information by accumulating majority carriers in a floating channel body of an FET formed on a silicon on insulator (SOI) or the like has been proposed (refer to Japanese Unexamined Patent Application Nos. 2003-68877 and 2002-246571).
An FBC has a main gate for forming a channel on the top face side of a channel body and an auxiliary gate formed so as to be capacitively coupled on the under face side.
There are a memory cell which is formed on a partially depleted SOI (PD-SOI) (refer to Japanese Patent Publication Laid-Open Nos. 2003-68877 and 2002-246571) and a memory cell which is formed on a fully depleted SOI (FD-SOI) (refer to Japanese Patent Publication Laid-Open No. 2003-31693). The latter memory cell is an FBC which is applicable even to a situation such that a transistor is becoming smaller and a silicon film of an SOI is becoming thinner.
In an FBC, generally, a fixed capacity is necessary for the channel body in order to assure a memory signal amount. One of options is a method of forming a buried oxide film (BOX) thinly and providing the capacitance between the channel body and a substrate. The potential of the substrate right below an FBC array is requested to be a negative potential so that holes can be accumulated in the channel body.
However, when the potential of the substrate under a transistor in a peripheral circuit, particularly, a PFET in the peripheral circuit becomes a negative potential, since the buried oxide film is thin, a back channel of the PFET is turned on and it causes a problem such that a normal transistor operation is disturbed.
On the other hand, in the case of forming an FBC on an FD-SOI, it is unclear how to design a transistor of a logic circuit in the case where both a peripheral circuit of a memory and an FBC memory are mounted.
Particularly, when both a P-type FET (PFET) and an N-type FET (NFET) are formed on a very thin silicon film and a substrate voltage is set to 0V in a normal fashion, and the absolute value of the threshold voltage of a PFET of an N-type polysilicon gate is too high, an NFET becomes a depletion type (a field effect transistor having a negative threshold voltage), so that practical use becomes impossible. Since the threshold voltages change depending on the thickness of a silicon film, in the case of a very thin silicon film, a subtle change in the thickness of the silicon film results in a large change in a threshold voltage, and it causes a problem such that a stable operation of the device is disturbed.